`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/11/20 20:01:30
// Design Name: 
// Module Name: rgmii2gmii_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module rgmii2gmii_top(
    //mac gmii
    input                       i_gmii_clk          ,  
    input                       i_gmii_rst          ,
    output  [7:0]               o_gmii_rxdata       ,
    output                      o_gmii_rxvalid      ,
    input   [7:0]               i_gmii_txdata       ,
    input                       i_gmii_txvalid      ,

    //phy rgmii
    input   [3:0]               i_rgmii_rxd         ,
    input                       i_rgmii_rxctl       ,
    input                       i_rgmii_rxc         ,
    output   [3:0]              o_rgmii_txd         ,
    output                      o_rgmii_txctl       ,
    output                      o_rgmii_txc         
);

    wire                        gmii_clk_phy        ;
    wire [7 :0]                 gmii_rxdata         ;
    wire                        gmii_rxvalid        ;
    wire [7 :0]                 gmii_txdata         ;
    wire                        gmii_txvalid        ;  

// ila_32BIT ila_32BIT_top (
// 	.clk(gmii_clk_phy), // input wire clk


// 	.probe0({gmii_txvalid, gmii_txdata,gmii_rxvalid,gmii_rxdata}) // input wire [31:0] probe0
// );

/*====================================================================
Cross the clock domain from the rgmii receiver clock to the 125M clock 
given at the mac layer
=====================================================================*/
    gmii_ram_tx tx(
        .i_pre_clk              ( i_gmii_clk        ),
        .i_pre_data             ( i_gmii_txdata     ),
        .i_pre_valid            ( i_gmii_txvalid    ),

        .i_post_clk             ( gmii_clk_phy      ),
        .o_post_data            ( gmii_txdata       ),
        .o_post_valid           ( gmii_txvalid      )
    );

    gmii_ram_rx rx(
        .i_pre_clk              ( gmii_clk_phy      ),
        .i_pre_data             ( gmii_rxdata       ),
        .i_pre_valid            ( gmii_rxvalid      ),

        .i_post_clk             ( i_gmii_clk        ),
        .o_post_data            ( o_gmii_rxdata     ),
        .o_post_valid           ( o_gmii_rxvalid    )
    );

/*====================================================================
Convert the timing of the DDR RGMII interface to the timing of 
the SDR GMII interface
=====================================================================*/
    rgmii2gmii rgmii2gmii_inst0(
        .i_rgmii_rxd            ( i_rgmii_rxd       ),
        .i_rgmii_rxctl          ( i_rgmii_rxctl     ),
        .i_rgmii_rxc            ( i_rgmii_rxc       ),
        .o_rgmii_txd            ( o_rgmii_txd       ),
        .o_rgmii_txctl          ( o_rgmii_txctl     ),
        .o_rgmii_txc            ( o_rgmii_txc       ),
        .o_gmii_clk             ( gmii_clk_phy      ),
        .o_gmii_rxdata          ( gmii_rxdata       ),
        .o_gmii_rxvalid         ( gmii_rxvalid      ),
        .i_gmii_txdata          ( gmii_txdata       ),
        .i_gmii_txvalid         ( gmii_txvalid      )
    );




endmodule
